Introduction to FPGA Part 5 - Finite State Machine (FSM)
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Design a Finite state machine (FSM) using one-hot coding that will detect a 0111 binary sequence on an input X. Two outputs Z0 and Z1 can be assumed to both be initially at 0. When the input sequence has been detected, the FSM will wait for one clock pulse. If X=1 then output Z0 is set to 1, otherwise if X=0, output Z1 is set to 1. After a further clock pulse both outputs Z0 and Z1 are set to 1. The FSM then resets after the next clock pulse, and restarts checking for a next binary input sequenc
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